DK-DEV-5SGXEA7N【PDF 194/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51008

2014.01.10

Guideline: Using DQ/DQS Pins

7-3

? You cannot use a x4 DQ/DQS group for memory interfaces if any of its members are used as RZQ pins

for OCT calibration.

? There is no restriction on using x8/x9, x16/x18, or x32/x36 DQ/DQS groups that include the x4 groups

whose pins are used as RZQ pins because there are enough extra pins that you can use as DQS pins.

Note: For the x8, x16/x18, or x32/x36 DQ/DQS groups whose members are used as RZQ pins, Altera

recommends that you assign the DQ and DQS pins manually. Otherwise, the Quartus II software

might not be able to place the DQ and DQS pins, resulting in a “ no-fit ” error.

DQ pins can be bidirectional signals, as in DDR3 and DDR2 SDRAM, and RLDRAM II common I/O

interfaces, or unidirectional signals, as in QDR II+ and QDR II SRAM, and RLDRAM II separate I/O devices.

Connect the unidirectional read-data signals to Stratix V DQ pins and the unidirectional write-data signals

to a different DQ/DQS group than the read DQ/DQS group. You must assign the write clocks to the

DQS/DQSn pins associated to this write DQ/DQS group. Do not use the CQ/CQn pin-pair for write clocks.

Note: Using a DQ/DQS group for the write-data signals minimizes output skew, allows access to the write-

leveling circuitry (for DDR3 SDRAM interfaces), and allows vertical migration. These pins also have

access to deskewing circuitry (using programmable delay chains) that can compensate for delay

mismatch between signals on the bus.

Reading the Pin Table

For the maximum number of DQ pins and the exact number per group for a particular Stratix V device,

refer to the pin table in the Stratix V Device Pin-Out Files page of the Altera website. In the pin tables, the

DQS and DQSn pins denote the differential data strobe/clock pin pairs, while the CQ and CQn pins denote

the complementary echo clock signals. The pin table lists the parity, DM, BWSn, NWSn, ECC, and QVLD

pins as DQ pins.

In the Stratix V pin tables, DQSn and CQn pins are marked separately. Each CQn pin connects to a DQS

logic block and the phase-shifted CQn signals go to the negative half cycle input registers in the DQ IOE

registers.

The DQS and DQSn pins are listed respectively in the Stratix V pin tables as DQS XY and DQSn XY . X indicates

the DQ/DQS grouping number and Y indicates whether the group is located on the top (T), bottom (B), left

(L), or right (R) side of the device. The DQ/DQS pin numbering is based on the x4 mode.

The corresponding DQ pins are marked as DQ XY , where X indicates which DQS group the pins belong to

and Y indicates whether the group is located on the top (T) or bottom (B) side of the device.

For example, DQS1T indicates a DQS pin located on the top side of the device. The DQ pins belonging to

that group are shown as DQ1T in the pin table.

External Memory Interfaces in Stratix V Devices

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